1. Field of the Invention
The present invention relates to a semiconductor device, a signal processing system using the same, and a calculation method therefor and, more particularly, to a semiconductor device which can perform parallel calculation processing, a signal processing system using the same, and a calculation method therefor which can improve the calculation speed.
2. Related Background Art
In a semiconductor device that performs parallel calculation processing, since the circuit scale increases in progression as the number of signals to be subjected to parallel calculations increases, the manufacturing cost increases, and the yield is lowered. Due to an increase in delay amount of a signal transmitted via, e.g., wiring lines or due to an increase in the number of times of calculations in the circuit upon an increase in circuit scale, the operation speed decreases. In addition, the consumption power often increases considerably due to the calculation processing.
FIG. 1 shows an example of an absolute value calculation circuit as a kind of calculation processing. Referring to FIG. 1, the circuit comprises an A/D converter 101 for receiving analog signals A and B, subtracters 102-1 and 102-2 respectively receiving digital values of the signals A and B and outputting their differences, a selector 103 for selecting one of the outputs from the subtracters, and a comparator 104 for comparing the output from the selector 103 with a reference signal, and performs an absolute value calculation.
In this circuit, the analog signals A and B are A/D-converted into digital data by the A/D converter 101, and the digital data are then subjected to subtractions (SUB). At this time, the subtractions A-B and B-A are performed for the signals A and B, and thereafter, the selector (SEL) 103 extracts a signal with a positive sign (M. Yamashita et. al. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23 NO. 4 p. 907, 1988). Furthermore, in order to discriminate whether or not the extracted value is larger than a predetermined value C, the comparator 104 is connected to the selector.
However, when real-time processing of, e.g., dynamic images is to be performed, the number of calculation steps such as compression expansion, thin-out interpolation, DCT inverse DCT, quantization dequantization, and the like is very large. In addition, when the number of gradation levels increases to obtain images with higher reality, the number of bits increases, i.e., the circuit scale increases in progression, resulting in low processing speed.